Jesse PrusiPrincipal ASIC Verification Engineer
Greater Minneapolis-St. Paul Area
Principal ASIC Verification Engineer
Sr. Staff Digital Design and Verification Engineer
Staff ASIC Verification Engineer
ASIC/FPGA Verification Engineer Sr.
Research Assistant
Test Engineering Intern
Student Engineer
University of Minnesota-Twin Cities
Stevens Institute of Technology
University of Minnesota-Twin Cities
Recommendations: 3
ASIC/FPGA Functional Verification Architecture
VHDL
Verilog
SystemVerilog
ModelSim
TCL
Functional Verification
FPGA