Top Sr. Design Engineers in San Jose, California
Piyush Kaushal
Risk Analyst, Risk Analytics & Forecasting (Seller Risk Management)
San Jose, California
Risk Analyst, Risk Analytics & Forecasting (Seller Risk Management)
Sr. Product Manager , Value added Consumer Products at PayPal
Design Engineer
Manager , Product Personalization & Analytics
Manager, Product & Analytics ( FMX/Growth Team)
Sr. Product Analyst
Analyst, Consumer Risk Management (Global Business Analytics)
Sr. Design Engineer
Indian Institute of Technology, Madras
Gossner college Ranchi
Recommendations: 6
SQL
SAS/SQL
Business Analysis
Risk Management
Fraud Analysis
Collections
Rally
Business Strategy
k****[email protected]
p****[email protected]
Jayant Mittal
Staff Software Engineer
San Jose, California
Staff Software Engineer
Sr. Design Engineer
Lead MTS
Senior Research Engineer
Senior Member Technical Staff
Senior Staff Design Engineer
Staff Design Engineer EMAC/PCIe groups of APD
Santa Clara University
Indian Institute of Science
St. Stephens College, Delhi University, India
Recommendations: 2
PCIe
FPGA
Xilinx
IP
RTL design
Verilog
Perl
VHDL
j****[email protected]
j****[email protected]
Varun Malhotra
FPGA Design Engineer
San Jose, California
FPGA Design Engineer
Sr. Design Engineer
Test Engineering Intern
Digital Design Intern
Sr. Test. Engineer
San Diego State University
Kurukshetra University
Recommendations: 1
Debugging
FPGA
RTL design
Integrated Circuit...
VHDL
Verilog
Xilinx SDK
Xilinx IDE
m****[email protected]
Asif N
Sr. Design Engineer
San Jose, California
Sr. Design Engineer
Sr. Software Engineer
Research and Design Intern
Software Engineer
Lead Graduate Technical Student Assistant
Software Engineer II
Software Engineer I
Embedded Software Developer
Validation Engineer
Freelance Software Engineering Consultant
Technical Support Executive, Tier 2
San Jose State University
Visvesvaraya Technological University
Recommendations: 0
Electric Vehicles
LaTeX
C
C++
Python
Java
C#
Microcontrollers
g****[email protected]
Andy Le
Director of Product Engineering
San Jose, California
Director of Product Engineering
Engineering Consultant
Senior Staff Design Engineer
Director of Engineering (Physical Design/SOC Methodology/CAD)
Director of CAD and Design Methodology
Sr. Manager of CAD/Methodology/Library Development
Sr. Design Engineer
Sr. Design Engineer
Member of Technical Staff
Sr. Design Engineer
EDA Tools/IPs/Languages/Skills
Senior Staff Engineer
San Jose State University
San Jose State University
UC Berkeley College of Engineering
Recommendations: 0
IC
EDA
Semiconductors
ASIC
SoC
Physical Design
Mixed Signal
Static Timing Analysis
a****[email protected]
Surinder S.
Sr. MTS Design Engineer
San Jose, California
Sr. MTS Design Engineer
Sr. Design Engineer
Sr. Staff Design Engineer
SCPD, Stanford University
Delhi University
Delhi University
Recommendations: 0
SERDES
I/O
Physical Design
2.5D IC Design
HSSI Architecture
Power Integrity
Signal Integrity
Analog Circuit Design
s****[email protected]
Marius Corbu
Sr. Design Engineer
San Jose, California
Sr. Design Engineer
Principal Engineer
Sr. Design Engineer Consultant
Staff Design Engineer
Sr. Design Engineer
Senior Staff Engineer
Staff Engineer
Design Engineer
University of South Carolina
Recommendations: 0
RTL design
Microarchitecture
Verification
Timing Closure
Formal Verification
Verilog
VHDL
m****[email protected]
Deepa Thali
Sr.Staff Design Engineer
San Jose, California
Sr.Staff Design Engineer
Sr. Design Engineer
Physical Design Engineer
Sr.Staff Engineer
Staff Design engineer
The University of Texas at Arlington
Andhra University
Recommendations: 0
SoC
ASIC
RTL design
Logic Synthesis
Timing Closure
IC
Physical Design
Debugging
d****[email protected]
Wei-Jen Huang
Design Engineer
San Jose, California
Design Engineer
Sr. Manager, Design Engineering
Sr. Design Engineering Manager
Sr. Mixed signal design engineer
Sr. Design Engineer
USC
University of California, Los Angeles
National Chiao Tung University
Recommendations: 0
Mixed Signal
IC
PLL
Semiconductors
Verilog
Circuit Design
ASIC
Analog
Qiujie Dong
Deep Learning HW Engineer
San Jose, California
Deep Learning HW Engineer
Technical Leader
Sr. Design Engineer
Texas A&M University
Tsinghua University
Recommendations: 0
q****[email protected]
Mike Hilldoerfer
R&D Manager
San Jose, California
R&D Manager
Design Engineer
Regulatory Affairs Manager/Director
Sr. Design Engineer
Vice President, RA/QA and Clinical Sciences
Indiana University Bloomington
Rensselaer Polytechnic Institute
Penn State University
Recommendations: 0
CE marking
R&D
Quality Management
Design Control
Capital Equipment
Commercialization
Process Improvement
Regulatory Affairs
m****[email protected]
m****[email protected]
Boris L.
Sr. ASIC Engineering Manager
San Jose, California
Sr. ASIC Engineering Manager
Sr. ASIC Design Engineer
Staff ASIC Design Engineer
Sr. Staff Design Engineer
Lead ASIC Design Engineer
Sr. Design Engineer
Portland State University
University of Houston
Georgia Institute of Technology
Recommendations: 0
