Puneet ChauhanFull Chip Lead for Verification & Validation
Santa Clara, California
Full Chip Lead for Verification & Validation
Senior Staff Engineer, Lead Verification/Validation
Principal Engineer, Verification Lead
ASIC Verification Manager
ESL Performance Modeling, Principal Engineer
Verification Lead/Architect
SOC Verification, Principal Engineer
ASIC Verification Manager
Queen's University
Indian Institute of Technology, Madras
Kendriya Vidyalaya
Recommendations: 0
ASIC
SoC
Functional Verification
Firmware
Verilog
RTL design
SystemVerilog
ARM