Top Senior Member Technical Staffs in San Jose, California
Alexander K.
Software Architect, People Manager @ CX Unity
San Jose, California
Software Architect, People Manager @ CX Unity
Senior Technical Lead, People Manager @ Google Cloud Platform
Technical Lead, People Manager @ Google Cloud Platform
Software Architect, People Manager
Principal Member Technical Staff
Lead Member of Technical Staff
Senior Member Technical Staff
Director of Engineering & Co-Founder
J2EE senior developer; Wrike.com developer;
Software developer
J2EE team lead at Muranosoft; contractor
J2EE developer
Developer
Kharkiv national university of radioelectronics
Alexandria regular school
Recommendations: 30
Spring
SOA
XML
JUnit
Memcached
Ant
Agile Methodologies
J2EE
a****[email protected]
Himanshu Singh
Domain Expert
San Jose, California
Domain Expert
MTS2 - Software Engineer
Senior Software Engr
Software Engr
Software Engr
Programmer
Sr Risk Platform Architect
Programmer Analyst
Senior Member Technical Staff
Senior Compliance Platform Architect
Mahatma Jyotiba Phule (MJP) Rohilkhand University
Recommendations: 15
Java
C++
Visual C++
Oracle SQL
MongoDB
Databases
Visio
Agile Methodologies
h****[email protected]
Chetan Punekar
Senior Member Technical Staff
San Jose, California
Senior Member Technical Staff
Associate Member Technical Staff
Member Technical Staff
Student Assistant
Research Intern
Research Assistant
San Jose State University
University of Pune
University of Pune
Recommendations: 8
SOA
TIBCO
Unix
Cloud Computing
OpenStack
RESTful WebServices
Core Java
Performance Tuning
c****[email protected]
c****[email protected]
Gaurav Gupta
Software Engineer
San Jose, California
Software Engineer
Intern
Software Engineer
Technical Leader
Senior Member Technical Staff
Committer and PMC member Apache Apex
Committer and PPMC member Apache Apex (incubating)
Lead Technical Architect - Big Data Labs
Member Technical Staff
Software Engineer
Member Technical Staff
Tech Lead
Indian Institute of Technology, Delhi
D.A.V Public School
Recommendations: 2
Distributed Systems
Core Java
Web Services
MapReduce
Hadoop
Solr
J2EE
Pig
g****[email protected]
Jayant Mittal
Staff Software Engineer
San Jose, California
Staff Software Engineer
Sr. Design Engineer
Lead MTS
Senior Research Engineer
Senior Member Technical Staff
Senior Staff Design Engineer
Staff Design Engineer EMAC/PCIe groups of APD
Santa Clara University
Indian Institute of Science
St. Stephens College, Delhi University, India
Recommendations: 2
PCIe
FPGA
Xilinx
IP
RTL design
Verilog
Perl
VHDL
j****[email protected]
j****[email protected]
Anuj Tripathi
Principal Software Engineer
San Jose, California
Principal Software Engineer
Senior Member Technical Staff
Indian Institute of Technology, Bombay
Uttar Pradesh Technical University
Recommendations: 1
Distributed Systems
iOS Development
Objective-C
C
Cluster Development
Linux
GDB
Algorithms
a****[email protected]
a****[email protected]
Varun Agarwal
Summer Intern
San Jose, California
Summer Intern
AR/VR Engineer
Senior ASIC Design Engineer
Engineer
Senior Member Technical Staff
Staff ASIC Design Engineer
Cornell University
Indian Institute of Technology (Banaras Hindu University), Varanasi
Recommendations: 0
C
Perl
VHDL
C++
Simulations
Verilog
Shell Scripting
Computer Architecture
a****[email protected]
Sahaya Albert
Senior Software Engineer
San Jose, California
Senior Software Engineer
Software Engineer
Programmer Analyst
Senior Member Technical Staff
Principal Software Engineer
Apple Media Products
Manonmaniam Sundaranar University
National Engineering College
Recommendations: 0
a****[email protected]
Anshuman Mittal
Senior Manager, Hardware Development
San Jose, California
Senior Manager, Hardware Development
Consultant
CPU/SOC Verification Manager
Senior Manager
Associate Project Manager
Power/Perf Architect (Sr. Manager)
Senior Member Technical Staff
Senior Software Engineer
Santa Clara University
Netaji Subhas Institute of Technology
Recommendations: 0
Testbench Architect (using UVM, verilog, C/C++)
System Verilog
Microprocessor Architecture (MIPS, ARM, PowerPC)
Verilog
C/C++
Graphics Processors
Functional, Chip & System Verification
Memory System Verification (L1/L2 Cache, Memory coherence, MOESI/MESI/MEI)
a****[email protected]
a****[email protected]
Hari Poolla
Senior Member Technical Staff - Architect
San Jose, California
Senior Member Technical Staff - Architect
Lead SOA Architect, Financial Services
Software Engineer
Systems Analyst
Indian Institute of Technology, Bombay
National Institute of Technology Warangal
New Colony Mpl High School
Recommendations: 0
SOA
Java Enterprise Edition
Solution Architecture
Web Services
Agile Methodologies
Enterprise Architecture
Websphere
SDLC
