Top Member of Technical Staffs in Austin, Texas

Marcilio Mendonca

Sr. Solutions Developer, Global Accounts

Austin, Texas

Sr. Solutions Developer, Global Accounts

System Analyst

Senior Member of Technical Staff

Sr. Global AWS Consultant

Lecturer

PhD Student & Post-Doc Fellow, Computer Science

Software Team Lead

Software Development Engineer

Software Team Lead

Sr. AWS Consultant

University of Waterloo

Pontifícia Universidade Católica do Rio de Janeiro

Federal University of Ceara

Recommendations: 7

m****[email protected]

John Xu

Senior Director of Engineering

Austin, Texas

Senior Director of Engineering

IP Design Manager, NMG

VP HW R&D

Founder and CEO

Member of Technical Staff

SOC Design Manager, NMG

Senior Member Technical Staff, PowerPC SOC Architect

Systems and Architecture Director, DNG

Senior Design Engineer

CTO

The University of Texas at Austin

Rensselaer Polytechnic Institute

University of Science and Technology of China

Recommendations: 4

SoC

Codecs

DSL

ASIC

Embedded Systems

Project Management

Engineering Management

z****[email protected]

Arturo Martin-de-Nicolas

President

Austin, Texas

President

Software Development Contractor

Senior Programmer

Senior Software Developer

Member of Technical Staff

Senior Software Developer

Contract Programmer

Principal Engineer

Sr Engineer

Senior Software Engineer

Rice University

Recommendations: 3

C/C++ STL

Parallel Programming

x86 Assembly

x86 Microcode

Multithreading

Creative Problem Solving

Concurrency

X86

a****[email protected]

Will Hong

Sr. Engineering Manager, HW/SW Platforms

Austin, Texas

Sr. Engineering Manager, HW/SW Platforms

Hardware Engineer

Design Engineer

Microprocessor Validation Engineer

Digital Design Engineer

Staff Design Engineer/Manager of Mixed-Signal Methodology

Staff Design Engineer

Principal Solutions Engineer

Design Engineer

Member of Technical Staff

The University of Texas at Austin

University of Illinois at Urbana-Champaign

Recommendations: 3

ASIC

SoC

RTL Design

Verilog

SystemVerilog

EDA

Mixed Signal

Debugging

w****[email protected]

Lincoln Nunes

Member of Technical Staff

Austin, Texas

Member of Technical Staff

Universidade Metodista de Piracicaba

Universidade Estadual de Campinas

Recommendations: 3

ASIC

SoC

Microprocessors

Verilog

Integrated Circuit Design

RTL design

Functional Verification

l****[email protected]

Mark Young

Senior Software Engineer

Austin, Texas

Senior Software Engineer

Member of Technical Staff

Recommendations: 3

Software Design

Software Engineering

Debugging

Software Development

C++

Distributed Systems

Object Oriented Design

m****[email protected]

Peter Droppa

Member of Technical Staff

Austin, Texas

Member of Technical Staff

Principal Engineer

Staff Design Engineer

University of Illinois at Urbana-Champaign

Recommendations: 2

Testing

Test Automation

Test Planning

Semiconductor Manufacturing

Java

XML

Performance Testing

Cost Reduction

p****[email protected]

Henning Spruth

Researcher

Austin, Texas

Researcher

Senior Member of Technical Staff

Standard Cell Library Benchmarking Lead

Design System Architect

Principal Engineer

Technical University Munich

Recommendations: 2

BIST

Verilog

RTL Design

Functional Verification

DFT

Logic Design

Physical Design

SystemVerilog

h****[email protected]

Ryan Hibbeler

Applications Engineering Co-Op

Austin, Texas

Applications Engineering Co-Op

Sr. Software Engineer

Lead Software Engineer

Lead Member of Technical Staff

Technical Solutions Engineer

Sr. Software Engineer

Software Engineer

Applications Engineer

Software Engineer

The University of Texas at Austin

Recommendations: 2

C++

SQL

Ruby

Perl

ASP.NET MVC

XML

Shams Pirani

Engineer, Staff

Austin, Texas

Engineer, Staff

Member of Technical Staff, IC Design

Teaching Assistant

Notebook Intern

Teaching Assistant

Operations and Maintenance Engineer

University of California San Diego

National Institute of Technology

Recommendations: 1

VHDL

Verilog

ModelSim

FPGA

Cadence Virtuoso

SystemVerilog

Analog

Logic Synthesis

Bob Renninger

Senior RF IC Design Engineer

Austin, Texas

Senior RF IC Design Engineer

Member of Technical Staff

Analog IC Design Engineer

Senior Member of Technical Staff

Senior Analog IC Design Engineer

Senior Member of Technical Staff

University of Arkansas at Little Rock

Michigan State University

Recommendations: 1

Mixed Signal

Analog

Analog Design

PLL

Integrated Circuit Design

Cadence Virtuoso

Analog Circuit Design

Jeff Waller

Member of Technical Staff

Austin, Texas

Member of Technical Staff

Senior Design Engineer

Member of Technical Staff

Senior Hardware Engineer

ASIC Design

SoC Architecture

SoC micro-architect

SoC Design/Arch

The University of Texas at Arlington

Recommendations: 1

SoC

ASIC

RTL design

Low-power Design

Power Management

PCIe

PCI-X

PCI Standards

Alexei Duhovich

Principal Engineer

Austin, Texas

Principal Engineer

Member of Technical Staff II

Project Engineer Assistant - Co-op

Electrical Engineer - Co-op

Principal Engineer II

University of Maryland College Park

Walden University

Drexel University

Recommendations: 0

VHDL

Verilog

Perl

Shell Scripting

System Verilog

UVM

SystemVerilog

a****[email protected]

Ruoxin Jiang

Staff Design Engineer

Austin, Texas

Staff Design Engineer

Member of Technical Staff

Design Engineer

Staff Design Engineer

Oregon State University

Fudan University

Recommendations: 0

Mixed Signal

Analog

Delta Sigma Modulator Design

High Speed A/D Design

Analog Signal Conditioning Circuit Design

Lisa Su

Senior Vice President & CTO

Austin, Texas

Senior Vice President & CTO

SVP & GM, Networking and Multimedia Group

VP, Semiconductor R&D

Member of Technical Staff

President & CEO

SVP & GM, Global Business Units

Recommendations: 0

l****[email protected]

Ralee Turlington

Application Developer

Austin, Texas

Application Developer

Senior Member of Technical Staff

Data Architect

Database Engineer/ Business Intelligence Developer

Database Developer/Data Wrangler

Computer Lab Assistant

Data Architect/Data Engineer

Database Developer/Database Administrator

Database Developer

Drexel University

Recommendations: 0

t****[email protected]

Seth Herstad

Member of Technical Staff

Austin, Texas

Member of Technical Staff

Senior Staff Engineer

Senior Engineer

Design Engineer 2

Teaching Assistant in ECE department

Student Employee in Office of Student Financial Aid

Intern

Co-op with Systems Engineering Group

Co-op with Technical Assistance Center

University of Illinois at Urbana-Champaign

Recommendations: 0

SystemVerilog

Perl

Verilog

C++

Functional Verification

RTL verification

Computer Architecture

Microprocessors

f****[email protected]

Joe Chien

Graduate Student Researcher

Austin, Texas

Graduate Student Researcher

Undergraduate Researcher

RF/Analog Mixed Signal IC design

Senior Member of Technical Staff (PMIC for Mobile Communication)

Senior Member of Technical Staff (RFIC Design)

Member of Technical Staff (RFIC Design)

Graduate Student Instructor

Analog Mixed Signal Design Engineer

Principal Member of Technical Staff (Cloud & Data Center Business Unit)

Staff Engineer (RF & Analog Mixed Signal IC Design)

University of California, Berkeley

University of California, Irvine

Recommendations: 0

CMOS

Mixed Signal

Analog

Simulations

Integrated Circuit...

Hesham Abdelghany

OPC Development Engineer

Austin, Texas

OPC Development Engineer

CAE, Staff Engineer

Senior Member of Technical Staff

Design For Testability Consultant

IC Design Consultant

IPD

Cairo University

Recommendations: 0

EDA

Integrated Circuit Design

Semiconductors

ASIC

DFT

Simulations

TCL

h****[email protected]

Shubham Saurav

Senior Software Engineer

Austin, Texas

Senior Software Engineer

Member of Technical Staff (Software Engineer)

Java Technical Lead

Software Developer

Software Engineer

B. K. Birla Institute of Engineering & Technology, Pilani

Thakur college of science and commerce

Recommendations: 0

Amit Apte

Principal Member of Technical Staff

Austin, Texas

Principal Member of Technical Staff

Senior Design Engineer

Senior Member of Technical Staff

Design Engineer 2

Member of Technical Staff

The University of Texas at Austin

University of Maryland

University of Mumbai

Recommendations: 0

C/C++ STL

Verilog

SystemVerilog

Perl

X86

x86 Assembly

Functional Verification

Computer Architecture

a****[email protected]

Jay Connelly

recharging

Austin, Texas

recharging

Director of Software Engineering

Member of Technical Staff

Director of Advanced Visual Computing

Sr. Director of Austin Technology Center

General Manager of Ranier

Staff architect

Sr. Manager, Server Power and Performance Optimizations

Director of Heterogeneous System Software

Sr. Director of Research and Development

Stanford University

The University of Texas at Arlington

Recommendations: 0

Vibhor Mittal

co-op array and mixed signal

Austin, Texas

co-op array and mixed signal

Senior Member of Technical Staff

Co-Op Design Engineer

Member of Technical Staff

Senior Design Engineer

Design Engineer

Volunteer / Developer

Research Assistant

Arizona State University

Visvesvaraya Technological University

Recommendations: 0

EDA

Circuit Design

Perl

SRAM

Python

Verilog

Cadence Virtuoso

VLSI

v****[email protected]

David Kaplan

SDE Intern

Austin, Texas

SDE Intern

Security Architecture Fellow

Principal Member of Technical Staff

University of Illinois at Urbana-Champaign

Recommendations: 0

Microcode

Security

Verilog

x86

ARM

Cryptography

Architecture

CPU design

d****[email protected]

James Walker

Software Engineer

Austin, Texas

Software Engineer

Senior Member of Technical Staff

Systems Programmer

Software Engineer

Senior Staff Software Developer

Software Engineer

Senior Software Engineer

Systems Programmer

Senior Software Developer

Texas A&M University

Baylor University

Recommendations: 0

Dan Hopper

MTS

Austin, Texas

MTS

Staff Engineer

Autopilot Sr. Staff Hardware Engineer

Principal Member of Technical Staff

North Carolina State University

Recommendations: 0

Microprocessors

Processors

Computer Architecture

Microarchitecture

CPU design

RTL design

Logic Design

ASIC

d****[email protected]

n****[email protected]

Wei Han

Staff Design Engineer, Digital Lead/Manager

Austin, Texas

Staff Design Engineer, Digital Lead/Manager

IC Design Manager

Member of Technical Staff

University of Minnesota-Twin Cities

Beijing Jiaotong University

University of Science and Technology of China

Recommendations: 0

Mixed Signal

ASIC

SoC

Semiconductors

Verilog

CMOS

Analog

h****[email protected]

Vasu Iyer

Principal Engineer and Technical Lead

Austin, Texas

Principal Engineer and Technical Lead

Senior Design Engineer

IC Designer

Project lead

Senior Design Engineer

Director - GPU

Member of Technical Staff

Senior Hardware Engineer

Senior Staff Engineer

University of Louisiana at Lafayette

Osmania University

Recommendations: 0

Physical Design

VLSI

Low-power Design

SoC

RTL design

ASIC

Verilog

Functional Verification

v****[email protected]

Tom Deelman

Graduate Research Assistant & Lab Head, Psycholinguistics Laboratory

Austin, Texas

Graduate Research Assistant & Lab Head, Psycholinguistics Laboratory

Member of Technical Staff - Human Factors

Director, User Experience/Usability

Sr. Manager, Client Usability

Director, Experience Design

Sr. Human Factors Engineer

Sr. Manager, Human Factors

Vice President, User Experience

Sergeant (E-5)

Undergraduate Research Assistant, Animal and Human Behavior Laboratory,

Recommendations: 0

Usability Testing

Mobile Devices

User Interface Design

Telecommunications

User Experience

Usability Engineering

User-centered Design

Heuristic Evaluation

t****[email protected]

Sivayya Ayinala

Design Engineer

Austin, Texas

Design Engineer

Senior Member of Technical Staff

Staff design engineer

Staff Design Engineer

Sr. Design Engineer

University of Louisiana at Lafayette

Jawaharlal Nehru Technological University

Recommendations: 0

SoC

ASIC

Static Timing Analysis

Verilog

Low-power Design

RTL design

Timing Closure

Jeffrey Steinheider

Product Marketing - Industrial and IoT Markets, Digital Networking

Austin, Texas

Product Marketing - Industrial and IoT Markets, Digital Networking

Senior Product Manager

General Manager Industrial Edge Processing Product Line

Director Product Marketing Industrial Applications Processors

Product Marketing - Small Cells, Wireless Access Division

Member of Technical Staff

Base Station Engineering Manager

Massachusetts Institute of Technology

Recommendations: 0

Wireless

LTE

Product Management

UMTS

Embedded Systems

GPRS

GSM

Woo Kim

Senior Staff Engineer

Austin, Texas

Senior Staff Engineer

Member of Technical Staff

Circuit Designer

Senior Design Engineer

Northeastern University

Yonsei University

Recommendations: 0

ASIC

Static Timing Analysis

VLSI

Logic Synthesis

Digital Signal...

Logic Design

Physical Design

Timing

w****[email protected]

t****[email protected]

Piyush Shivam

Member of Technical Staff

Austin, Texas

Member of Technical Staff

Duke University

The Ohio State University

Birla Institute of Technology and Science, Pilani

Recommendations: 0

p****[email protected]

Bipin Prasad

Consultant

Austin, Texas

Consultant

CPU Design

Senior Member of Technical Staff

Digital Design Engineer

Electrical Design Engineer

Physical Design Engineeer

Software Engineer

Senior Hardware Design Engineer

HBX | Harvard Business School

University of Southern California

Recommendations: 0

Physical Design

Analog

Integrated Circuit Design

SoC

ASIC

Verilog

p****[email protected]

Jordan Robison

Staff Site Reliability Engineer

Austin, Texas

Staff Site Reliability Engineer

Sr. Security Engineer / InfraSec Mentat

Bit Plumber / Member of Technical Staff

Senior Network Analyst

Network Engineer / IT Officer

Senior Network Security Engineer / Force Multiplier

Operations Engineer / Bit Plumber

Information Security Operations / Principal Packet Mangler / AVP

Information Security Administrator / Analyst

Senior Site Reliability Engineer

Lansing Community College

Baker College of Owosso

Recommendations: 0

Linux System Administration

Debian

cPanel

Red Hat Linux

Hosting

CentOS

Apache

Linux