Top IC Design Engineers in Santa Clara, California
Brian Hook
ASIC Design Engineer
Santa Clara, California
ASIC Design Engineer
Intern Software Engineer
ASIC Design Engineer
Design Verification Engineer
ASIC Design Engineer
ASIC Design Engineer
ASIC Design Engineer
Northeastern University
University of Central Florida
Recommendations: 7
SystemVerilog
Perl
Python
Verilog
SoC
Functional Verification
ASIC
RTL design
e****[email protected]
Ratnendra Pandey
IC Design Engineer
Santa Clara, California
IC Design Engineer
Hardware Engineer
Guest Lecturer
Project Associate
Member of Technical Staff
Applications Engineer
Silicon Design Engineer
Design Consultant RTL-Physical Design
Physical Design Engineer
Staff Corporate Application Engineer
San Jose State University
South Dakota State University
Punjab Engineering College
Recommendations: 3
ASIC
Static Timing Analysis
RTL design
TCL
Verilog
EDA
Debugging
Semiconductors
p****[email protected]
Sai Seshabhattar
Staff Application Engineer Emulation
Santa Clara, California
Staff Application Engineer Emulation
Application Consultant, Sr I
Application Consultant
Staff-I IC Design Engineer
Hardware design verification engineer
PDE- Co-op
The University of Texas at Arlington
Jawaharlal Nehru Technological University
Recommendations: 1
Logic Design
RTL coding
Computer Arithmetic
Functional Verification
RTL design
IC
Hardware Architecture
Integrated Circuit...
p****[email protected]
Navin Mohan
Application Engineer
Santa Clara, California
Application Engineer
Hardware Engineer
Intern - Hardware Engineering (Analog)
Staff Design Engineer
Silicon Architect Engineer (ASIC Design and Verification)
Analog Engineer/Component Design Engineer
Teaching Assistamt
SOC/ASIC Design Engineer
Arizona State University
Birla Institute of Technology and Science, Pilani
Sankara Vidhyalaya School
Recommendations: 1
VLSI
Verilog
n****[email protected]
n****[email protected]
Qiang Yu
Senior RF/mmWave IC Design Engineer
Santa Clara, California
Senior RF/mmWave IC Design Engineer
Staff RF/mmWave IC Design Engineer
Senior RF Design Engineer
Research Assistant
University of Virginia
Louisiana State University
Shanghai Jiao Tong University
Recommendations: 0
Matlab
Simulations
RF test
RFIC design
Mixed signal design
Micro-machining
Strain Sensor
Sensors
b****[email protected]
q*****@virginia.edu
Lavanya Subramanian
Staff Research Scientist
Santa Clara, California
Staff Research Scientist
Research Intern
ASIC Design Engineer
Research Scientist
SoC Architect at Facebook Reality Labs
Graduate Student Researcher
Research Intern
Silicon Performance Architect
Carnegie Mellon University
Madras Institute of Technology, Anna University
Saraswathi Vidyalaya
Recommendations: 0
C++
Analysis
Verilog
ASIC
VLSI
C
Embedded Systems
Python
l****[email protected]
Kushal Dave
ASIC Design Engineer
Santa Clara, California
ASIC Design Engineer
Graduate Student
Sr. Design Engineer
Staff Design Engineer
Design Engineer - Co-op
San Jose State University
Gujarat University
Recommendations: 0
d****[email protected]
Shougui Yang
ASIC Verification Engineer
Santa Clara, California
ASIC Verification Engineer
Senior ASIC Design Engineer
FPGA Designer
Logic Verification Engineer (Intern)
SoC Verification Lead, Staff Engineer
ASIC Design Verification Engineer
SoC Design Research Assistant
Peking University
Peking University
Recommendations: 0
OVM
UVM
FPGA
Verilog
System Verilog
Verification
DDR SDRAM
C++
y****[email protected]
Wanghua Wu
RFIC Senior Manager
Santa Clara, California
RFIC Senior Manager
RF/Analog IC Design Engineer
Analog/RF IC Engineer
Design Engineer Intern
Research Assistant (PhD candidate)
Delft University of Technology
Delft University of Technology
Fudan University
Recommendations: 0
CMOS
IC
Analog Circuit Design
Circuit Design
Analog
Matlab
Cadence Virtuoso
Integrated Circuit Design
w****[email protected]
Vishal Mehta
Senior ASIC Design Engineer
Santa Clara, California
Senior ASIC Design Engineer
Senior ASIC Design Engineer
Senior ASIC Design Engineer
ASIC Design Engineer
Project Assistant
ASIC Intern
University of Wisconsin-Madison
Indian Institute of Technology (Banaras Hindu University), Varanasi
The Indian School, Bahrain
Our Own English High School, Dubai, UAE
Recommendations: 0
RTL design
SoC
Verilog
ASIC
Debugging
Timing Closure
Functional Verification
VLSI
v****[email protected]
Ko-Chung Tseng
ASIC Design Manager
Santa Clara, California
ASIC Design Manager
Research Assistant
Teaching Assitant in EE577b (VLSI System Design)
Staff Design Engineer
Senior ASIC Design Engineer
Teaching Assistant in EE477L (MOS VLSI Circuit Design)
University of Southern California
University of Southern California
University of Southern California
Recommendations: 0
Verilog
SystemVerilog
Matlab
C++
Java
JavaScript
Cadence Ocean Script
Python
k****[email protected]
k****[email protected]
Liang Zhou
Senior RTL Design Engineer
Santa Clara, California
Senior RTL Design Engineer
ASIC Engineer 3
MTS ASIC Design Engineer
Design/Verification Intern
University of Arkansas at Fayetteville
Hubei University
Recommendations: 0
Computer Architecture
k****[email protected]
Ying Huang
Research Assistant
Santa Clara, California
Research Assistant
Assistant Radiation Safety Officer
Senior ASIC Design Engineer
Research Assistant
Teaching Assistant
University at Buffalo
Huazhong University of Science & Technology
Huazhong University of Science & Technology
Recommendations: 0
Cadence Virtuoso
Spices
C/C++, Verilog HDL, VHDL
Shell
Analog Circuit Design
Optical and CCD Detector Design
FPGA/CPLD, MCU, DSP
Circuit Design
h****[email protected]
Sreedhar Chikoti
Sr. ASIC Design Engineer
Santa Clara, California
Sr. ASIC Design Engineer
University of Southern California
University of Mumbai
Recommendations: 0
ASIC
Computer Architecture
RTL design
Verilog
SystemVerilog
Static Timing Analysis
VLSI
SoC
s****[email protected]
Mengzhao Wei
Analog/Mixed-Signal IC Design Engineer
Santa Clara, California
Analog/Mixed-Signal IC Design Engineer
Analog Design Engineer
Analog and Mixed Signal Design Engineer
Senior Analog Design Engineer
Analog Design Engineer
Engineering Rotation Program
State University of New York at Buffalo
Zhejiang Sci-Tech University, China
Middle School
Recommendations: 0
Cadence Virtuoso
Integrated Circuit...
VLSI
SPICE
VHDL
Analog
Cadence
Cadence Spectre
m*****@buffalo.edu
Ji Chen
Senior analog/RFIC Design Engineer
Santa Clara, California
Senior analog/RFIC Design Engineer
Senior Electrical Engineer
Senior analog/RFIC Design Engineer
Sr. RFIC design engineer
Staff Analog Design Engineer
University of Central Florida
Fudan University
Recommendations: 0
PLL
IC
CMOS
Analog
VCO
Circuit Design
Spectre
Mixed Signal
j****[email protected]
Danielle Morton
Research and Development/Analog VLSI Designer
Santa Clara, California
Research and Development/Analog VLSI Designer
Analog/Mixed-Signal Design Engineer
Mixed Signal IC Design Engineer
Intern QMT
Intern
ICBM Missile Maintenance Technician
PhD Candidate
Intern
University of California, Santa Barbara
University of California, Santa Barbara
University of California, Santa Barbara
Recommendations: 0
d****[email protected]
Nilotpal Sensarkar
Design Engineer
Santa Clara, California
Design Engineer
Staff ASIC Design Engineer
Summer Intern
Hardware
Senior Staff ASIC Design Engineer
Senior ASIC Design Engineer
Principal Engineer
Stony Brook University
Visvesvaraya Technological University
Sardar Patel Vidyalaya, New Delhi
Recommendations: 0
SystemVerilog
Verilog
RTL design
OOP
Microarchitecture
Hardware Security
Consumables
SoC
n****[email protected]
Jonathan Tam
5G RFIC: Sr. RFIC Design and SoC Integration Engineer
Santa Clara, California
5G RFIC: Sr. RFIC Design and SoC Integration Engineer
Analog I/O Layout Engineer (Intern)
RF Design & Test Engineer
Sr. RFIC Design Engineer
University of Toronto
Recommendations: 0
j****[email protected]
Joon Yoon
Principal Design Engineer
Santa Clara, California
Principal Design Engineer
Principal IC Design Engineer
Staff Engineer
Staff ASIC Engineer
Senior Design Engineer
Hardware Design Engineer
University of Pennsylvania
The Wharton School
Livingston High School
Recommendations: 0
ASIC
RTL design
Microprocessors
Hardware Architecture
Integrated Circuit Design
Mixed Signal
FPGA
SERDES
d****[email protected]
Jungyong Lee
IC Design Engineer
Santa Clara, California
IC Design Engineer
IC Design Engineer
Recommendations: 0
Physical Design
ASIC
Static Timing Analysis
Verilog
Perl
SoC
Microprocessors
CMOS
j****[email protected]
Silvia Maione
Contractor/analog-mixed signal design engineer
Santa Clara, California
Contractor/analog-mixed signal design engineer
System Engineer
Senior Analog-Mixed Signal Design Engineer
Analog Design Staff Engineer I
Analog IC Design Engineer
Sr IC Engineer
Data Science Career Track bootcamp student
Senior IC Design Engineer
Politecnico di Bari
Recommendations: 0
Analog Circuit Design
CMOS
IC
VLSI
Mixed Signal
Integrated Circuit Design
Analog
ASIC
s****[email protected]
Jian W.
PhD student
Santa Clara, California
PhD student
Senior ASIC Design Verification Engineer
Staff ASIC Design Engineer
Postdoctoral Research Associate
The University of Manchester
Beijing Institute of Technology
Huazhong University of Science and Technology
Recommendations: 0
b****[email protected]
Jay Patel
Software Engineering Intern
Santa Clara, California
Software Engineering Intern
Partner Technology Manager (TPM/SWE and external partnerships)
MBA Graduate Student
Experienced Commercial Leadership Program (ECLP) Summer Associate
Senior ASIC Design Engineer
ASIC Design Engineer
Teaching Assistant - Electrical & Computer Engineering Dept.
Research Assistant - Electrical & Computer Engineering Dept.
Research Assistant - Materials Science Engineering Dept.
Carnegie Mellon University - Tepper School of Business
Carnegie Mellon University
Carnegie Mellon University
Recommendations: 0
ASIC
RTL design
Verilog
Computer Architecture
SoC
Static Timing Analysis
Logic Design
EDA
j****[email protected]
Huaijin Chen
Analog Mixed-signal IC design consultant
Santa Clara, California
Analog Mixed-signal IC design consultant
Principal IC Design Engineer
Principal IC Design Engineer
Senior IC Design Engineer
Tsinghua University
École Polytechnique de Montréal
Recommendations: 0
ADC
DAC
Ultra Low Power Design
LDO
Sigma Delta
Data Converters
PLL
Bandgap References
h****[email protected]
Chengjun Wang
Senior Staff Engineer
Santa Clara, California
Senior Staff Engineer
ASIC Designer
ASIC Design Senior Staff/Manager
ASIC Design Engineer
Xidian University
Xidian University
Recommendations: 0
c****[email protected]
Sunghwan Kim
Staff RFIC Research Engineer
Santa Clara, California
Staff RFIC Research Engineer
Senior Analog RFIC Design Engineer
Staff RFIC Engineer
Analog Design Engineer
University of California, San Diego
University of Southern California
Seoul National University
Recommendations: 0
Ryan L.
Staff Hardware Engineer
Santa Clara, California
Staff Hardware Engineer
ASIC Design Engineer
Electrical Engineer Intern
Student Affair IT Assistant
University of California, Berkeley
University of California, Los Angeles
Recommendations: 0
C++
C
Electrical Engineering
Programming
Matlab
Circuit Design
SystemVerilog
Perl
Chia Tsai
PhD Student
Santa Clara, California
PhD Student
Intern
ASIC Design Engineer
Staff Design Engineer
Cornell University
National Cheng Kung University
National Cheng Kung University
Recommendations: 0
Surendra Kane
Hardware Development Engineer
Santa Clara, California
Hardware Development Engineer
ASIC Design Engineer
Staff Engineer, ASIC Development Engineering
Senior Engineer, ASIC Development Engineering
Hardware Engineering Intern
San Jose State University
Savitribai Phule Pune University
Recommendations: 0
Verilog
FPGA
NAND Flash
Functional Verification
ASIC
TCL
Python
SystemVerilog
Howie Yang
Senior IC Design Engineer
Santa Clara, California
Senior IC Design Engineer
Senior IC Design Engineer
Senior Communication System Design Engineer
Senior Staff Design Engineer
Sr. Principal Engineer
National Tsing Hua University
National Tsing Hua University
Recommendations: 0
SoC
ASIC
Verilog
Semiconductors
RTL design
Base band IC design for...
Transmit Beamforming
Multi-user Precoding
