Ratnendra PandeyIC Design Engineer
Santa Clara, California
IC Design Engineer
Hardware Engineer
Guest Lecturer
Project Associate
Member of Technical Staff
Applications Engineer
Silicon Design Engineer
Design Consultant RTL-Physical Design
Physical Design Engineer
Staff Corporate Application Engineer
San Jose State University
South Dakota State University
Punjab Engineering College
Recommendations: 3
ASIC
Static Timing Analysis
RTL design
TCL
Verilog
EDA
Debugging
Semiconductors