Top Digital Design Engineers in Austin, Texas

Will Hong
Sr. Engineering Manager, HW/SW Platforms
Austin, Texas
Sr. Engineering Manager, HW/SW Platforms
Hardware Engineer
Design Engineer
Microprocessor Validation Engineer
Digital Design Engineer
Staff Design Engineer/Manager of Mixed-Signal Methodology
Staff Design Engineer
Principal Solutions Engineer
Design Engineer
Member of Technical Staff
The University of Texas at Austin
University of Illinois at Urbana-Champaign
Recommendations: 3
ASIC
SoC
RTL Design
Verilog
SystemVerilog
EDA
Mixed Signal
Debugging
Henry Angulo
Verification Engineer
Austin, Texas
Verification Engineer
ASIC Design Verification Engineer
Digital Design Engineer
Engineering Development Student
ASIC Verification Engineer
ASIC Verification Engineer
ASIC Design Engineer
ASIC Design Engineer
ASIC Customer Support Engineer
Digital Design Engineer
Southern Methodist University
Phoenix Community Junior College
Recommendations: 1
Verilog
VHDL
Processors
PCIe
Perl
Assembly Language
Unix
Linux
Shafagh Kamkar
Graduate Research Assistant
Austin, Texas
Graduate Research Assistant
System-on-Chip Design Engineer
Graduate Teaching Assistant
Digital Design Engineer - Summer and Fall Co-op
Digital Design Engineer
Illinois Institute of Technology
KNTU
Recommendations: 0
C++
Matlab
VHDL
C
ModelSim
FPGA
Python
Java
Siva Bonasu
Staff Engineer-ASIC
Austin, Texas
Staff Engineer-ASIC
Senior Design Engineer
Design Engineer
CO-OP
Digital Design Engineer
Senior Staff Engineer
Arizona State University
Jawaharlal Nehru Technological University
Recommendations: 0
ASIC
Verilog
VHDL
Digital Signal Processors
SystemVerilog
Matlab
Audio Design
Mixed Signal
Chakrapani Saralaya
RTL Design Engineer
Austin, Texas
RTL Design Engineer
Digital Design Engineer
Research Assistant
Texas A&M University-Kingsville
Recommendations: 0
Matlab
Higher Education
Research
Student Affairs
Microsoft Office
Teaching
Public Speaking
PowerPoint
Sherif Morcos
Component Design Engineer
Austin, Texas
Component Design Engineer
Digital Design Engineer
Carnegie Mellon University
New York University - Polytechnic School of Engineering
Recommendations: 0
Static Timing Analysis
Verilog
Computer Architecture
RTL design
Logic Design
VLSI
TCL
Perl
Mike Babb
Lead Design Engineer
Austin, Texas
Lead Design Engineer
Design Engineer
Mixed-signal Design Engineer
Digital Design Engineer
Mississippi State University
Recommendations: 0
Mixed Signal
Integrated Circuit Design
ASIC
SystemVerilog
Primetime
RTL design
RTL
Low-power Design
Lior Greenberger
Hardware Engineer
Austin, Texas
Hardware Engineer
Staff Digital Design Engineer
Senior VLSI Design Engineer
Hardware Engineer
System Architect
VLSI Engineer
Tel Aviv University
Recommendations: 0
ASIC
SoC
VLSI
Verilog
RTL design
Ethernet
Hardware Architecture
Processors
Jaimin Mehta
Design Engineer
Austin, Texas
Design Engineer
Digital Design Engineer
Industrial Research Assistant
System Engineer & Digital Design
Senior Design Engineer
Digital Design & System Engineer
The University of Texas at Dallas
The University of Texas at Dallas
Dharmsinh Desai Institute of Technology
Recommendations: 0
Verilog
ASIC
Mixed Signal
SoC
VLSI
Integrated Circuit Design
IC
RTL design
Krishnan Balakrishnan
Sr Digital Design Engineer
Austin, Texas
Sr Digital Design Engineer
Design Engineer
Staff Design Engineer
Stanford University
Model Engineering College
Recommendations: 0
Verilog
SystemVerilog
Integrated Circuit Design
RTL Design
RTL verification
UVM
Debugging
Logic Synthesis
Eric Deal
Founder/VP Hardware Engineering
Austin, Texas
Founder/VP Hardware Engineering
Digital Design Engineer (E5)
Sr. Staff Engineer
Principle Member of Technical Staff - Digital Design Engineer
President
Principle Engineer
Principle Digital Design Engineer
Senior Digital Design Engineer
Texas A&M University
Recommendations: 0
SoC
RTL design
FPGA
RTL coding
Xilinx
Digital Design
Verilog
Hardware
Omar Torres
Staff Engineer
Austin, Texas
Staff Engineer
Senior Design Engineer
Senior Design Verification Engineer
Digital Design Engineer
Firmware Design Engineer
Product/Test Engineer
University of Texas at Austin
University of Puerto Rico at Mayaguez
Recommendations: 0
SoC
Debugging
IC
Mixed Signal
Semiconductors
Verilog
Embedded Systems
RTL design
Sumeer Arya
Staff Design Engineer
Austin, Texas
Staff Design Engineer
Design Engineer
Sr Digital Design Engineer
Senior Design Engineer
Associate Market Manager
Market Manager, Equity Options
Trading Operations
Design Engineer
Carnegie Mellon University
Georgia Institute of Technology
The University of Texas at Austin - Red McCombs School of Business
Recommendations: 0
C
Product Management
Trading Systems
Software Development
Semiconductors
Unix
C++
Equities
Gregory Knight
Electrical Engineer Co-op
Austin, Texas
Electrical Engineer Co-op
ASIC Developer
Hardware Engineer Intern
FPGA Design Engineer
FPGA Design Engineer
Corporate Application Engineer
Digital Design Engineer
Senior Corporate Applications Engineer
Hardware Design Engineer
Tuskegee University
St. Edward's University
Stanford University
Recommendations: 0
FPGA Design
Verilog HDL
Altera Quartus
Logic Design
SystemVerilog
Chandra Prakash
Internship
Austin, Texas
Internship
Internship
R&D IC Design Engineer
Digital Design Engineer
Internship
Analog Hardware Engineer
Senior RFIC Design Engineer
Staff Analog/RF Chip Design Engineer
Analog Design Engineer
The University of Texas at Austin
Indian Institute of Technology BHU, Varanasi
Recommendations: 0
Verilog
Integrated Circuit Design
VLSI
ASIC
RTL design
Cadence Virtuoso
Functional Verification
Mixed Signal
Curtis Rantz
RTL Verification Engineer (Contract)
Austin, Texas
RTL Verification Engineer (Contract)
Sr. Member of Tech Staff
Sr. RTL Design Engineer
Design Manager / Director of Operations
Sr. Digital Design Engineer
RTL Verification Engineer (Contract)
Logic Design Engineer (Contract)
Design Verification Engineer (Direct)
Digital Design Engineer (Contract)
RTL Verification Engineer (Contract)
Florida Institute of Technology
Recommendations: 0
Aniruddha S.
Digital Design Engineer
Austin, Texas
Digital Design Engineer
DSP Firmware Intern for Wireless Modems
Graduate Research Assistant
Georgia Institute of Technology
University of Mumbai
Recommendations: 0
Bipin Prasad
Consultant
Austin, Texas
Consultant
CPU Design
Senior Member of Technical Staff
Digital Design Engineer
Electrical Design Engineer
Physical Design Engineeer
Software Engineer
Senior Hardware Design Engineer
HBX | Harvard Business School
University of Southern California
Recommendations: 0
Physical Design
Analog
Integrated Circuit Design
SoC
ASIC
Verilog
Steve Vu
SMTS
Austin, Texas
SMTS
Digital RTL Design Engineer
MGTS Digital Design Engineer
Design/Test/Product Engineer
Senior Member of the Technical Staff
Senior Designer
Test/Product Engineer
ASIC Design Engineer
Texas A&M University
Recommendations: 0
ASIC
Verilog
Electrical Engineering
RTL design
IC
Abhishek Verma
Member Of Technical Staff
Austin, Texas
Member Of Technical Staff
Senior Digital Design Engineer
Digital Design Engineer
SoC Architect Intern
Student Worker at USC Career Center
Student Worker at Computer Science Department
Ericsson India Private Limited
Project Trainee
Industrial Training
University of Southern California
Y.M.C.A. Institute Of Engineering, Faridabad
DAV Public School, Sector-14, Faridabad
Recommendations: 0
Vaishali C.
Serdes Implementation Engineer
Austin, Texas
Serdes Implementation Engineer
Member of Technical Staff
Digital Design Engineer
RTL Synthesis/Timing Engineer
Lehigh University
Recommendations: 0
Ryo Inoue
Staff Digital Design Engineer
Austin, Texas
Staff Digital Design Engineer
ASIC Designer and Team Lead
IC Design Team Lead
Senior IC Designer
Senior IC Designer
IC Designer
Northwestern University
Northwestern University
Recommendations: 0