Top Design Engineers in Hillsboro, Oregon
Tani Aguayo
Post-Doc Research Associate
Hillsboro, Oregon
Post-Doc Research Associate
Research Associate
Volunteer
Electrical Engineer
Volunteer
Research Assistant
Analog Design Engineer
R&D Electrical Engineer
Universidad Autónoma de Madrid
Universidad Autónoma de Madrid
Universidad de Granada
Recommendations: 7
Geant4
Monte Carlo Simulation
ROOT
DSP
OOP
Device Characterization
VHDL
Electronics
e****[email protected]
Ashwin Hanchinal
Component Design Engineer
Hillsboro, Oregon
Component Design Engineer
Developer
University of Southern California
Visvesvaraya Technological University
Recommendations: 4
ASIC
ModelSim
Static Timing Analysis
Xilinx
Verilog
DFT
RTL coding
Digital Design
a****[email protected]
Piyush Hatolkar
IP integration and quality
Hillsboro, Oregon
IP integration and quality
Logic Design
Student Intern
Graduate Technical Intern (Analog Design)
Sr. RTL Design Engineer
Analog Design and Si debug
Technical Team Lead, IP integration and quality, handoff to BE
University of Southern California, LA
Government College of Engineering, Aurangabad
Recommendations: 3
Verilog
VHDL
SPICE
TCL
Perl
Matlab
Labview
Hardware Description Language
p****[email protected]
Debo Sekoni
DFT Contractor
Hillsboro, Oregon
DFT Contractor
ASIC Design Engineer
Sr. DFT Engineer
ASIC Field Design Engineer
IBM Burlington, VT
Northeastern University
Recommendations: 2
ASIC
DFT
Verilog
SoC
Semiconductors
EDA
ATPG
BIST
d****[email protected]
Thomas Brown
Senior Component Design Engineer
Hillsboro, Oregon
Senior Component Design Engineer
Senior Hardware Engineer
Senior Hardware Designer
Hardware Engineer II
Sr. Design Engineer
Senior Logic Designer
Contractor
Iowa State University
Iowa State University
Recommendations: 2
RTL Design
Debugging
RTL Coding
ASIC
RTL Verification
Microarchitecture
Verilog
VHDL
t****[email protected]
Gongquan Liu
System Design Engineer
Hillsboro, Oregon
System Design Engineer
Research Assistant
Software Engineer
R&D Engineer
University of Florida
Tongji University
Tianjin Nankai High school
Recommendations: 1
Cadence
Quartus
LTSpice
Xilinx
Agilent ADS
Matlab
PADS
Xilinx ISE
l****[email protected]
Scott Rosenbalm
Undergrad Intern - Technical
Hillsboro, Oregon
Undergrad Intern - Technical
Electrical Engineer
Tutor
Research Assistant
Electrical Engineering Design Intern
Freshman Mentor
Senior Hardware FPGA Design Engineer
Oregon State University
Recommendations: 1
Verilog
Python
PCB design
Java
SPICE
Perl
Hardware Architecture
Electrical Engineering
j****[email protected]
s****[email protected]
Arun Peri
Engineer, Analog/Mixed-Signal Design
Hillsboro, Oregon
Engineer, Analog/Mixed-Signal Design
Analog Design Engineer, Mixed Signal Development
Analog/Mixed Signal Design Engineer Sr.I
Analog IC Design Engineer
Research Associate, Columbia high-Speed and Mm-wave IC(CoSMIC) lab
Test and Characterization Engineer
Columbia University in the City of New York
National Institute of Technology Tiruchirappalli
Recommendations: 0
Analog
Analog Circuit Design
ADCs
DACS
Audio Codecs
Audio Amplifiers
Digital Circuit Design
Cadence Virtuoso
a****[email protected]
Kushal Sreedhar
Project Intern
Hillsboro, Oregon
Project Intern
Analog Design Engineer
Coop Engineer
Graduate Student
Undergraduate Intern
Georgia Institute of Technology
RNS Institute of Technology
Recommendations: 0
ModelSim
Spectre
Matlab
Orcad
SPICE
LTSpice
Virtuoso
RedHat
k****[email protected]
Mariano Aguirre
Engineering Manager
Hillsboro, Oregon
Engineering Manager
Research Scientist
Associated Professor
Associated Professor
HW Design Engineer
Associated Professor
Consultant/HW Design Engineer
Sr. HW Design Engineer
Sr. FPGA RTL Design Engineer
Engineering Manager
National Institute of Astrophysics, Optics and Electronics (INAOE-Mexico)
National Institute of Astrophysics, Optics and Electronics (INAOE-Mexico)
Instituto Politécnico Nacional
Recommendations: 0
m****[email protected]
Ning Zhang
Design Engineer
Hillsboro, Oregon
Design Engineer
Research Assistant
Intern Engineer
Teaching Assistant
Communication Enginee Co-op
RF/Analog IC Design Engineer
Researcher
Researcher
University of Florida
University of Wisconsin-Madison
South China University of Technology
Recommendations: 0
Analog Circuit Design
Cadence Virtuoso
IC
CMOS
Circuit Design
Agilent ADS
Simulations
RF
c****[email protected]
Edwin Castro
Engineer III
Hillsboro, Oregon
Engineer III
Software Development Engineer
Software Engineer III
Staff Software Developer
Build Engineer
Build Engineer
Software Design Engineer in Test 2
QA Engineer
Software Design Engineer
Oregon State University
Recommendations: 0
C#
WiX
PowerShell
Agile Methodologies
.NET
TFS
Visual Studio
Scrum
e****[email protected]
e****[email protected]
Vitaly Shevyakov
Electrical Engineer
Hillsboro, Oregon
Electrical Engineer
Electrical Design Engineer
Arizona State University
Gubkin Russian State University of Oil and Gas (former Moscow State Academy of Oil and Gas)
Gubkin Russian State University of Oil and Gas (former Moscow State Academy of Oil and Gas)
Recommendations: 0
Electrical Design
Electrical Maintenance
Electrical Equipment
Analitical
Problem Solving
AutoCAD
Electrical Engineering
Engineering
s****[email protected]
Rupesh Shelar
Senior Staff R&D Engineer
Hillsboro, Oregon
Senior Staff R&D Engineer
Senior Staff SoC Engineer
Principal Engineer
Staff Component Design Engineer
Senior Component Design Engineer
Senior Component Design Engineer
Grdaute Technical Intern
Graduate Technical Intern
Software Engineer
University of Minnesota-Twin Cities
Indian Institute of Technology, Bombay
Doctor Babasaheb Ambedkar Marathwada University
Recommendations: 0
VLSI
Low-power Design
Microprocessors
Circuit Design
Algorithms
Physical Design
ASIC
SoC
r****[email protected]
Senthil Sampath
Analog Design Manager
Hillsboro, Oregon
Analog Design Manager
Project Trainee
Analog Design Engineer
Graduate Student
Texas A&M University
Anna University
Recommendations: 0
Mixed Signal
Analog Circuit Design
Analog
PCIe
Processors
Cadence Virtuoso
VLSI
Verilog
e****[email protected]
George Matthew
Analog Engineer
Hillsboro, Oregon
Analog Engineer
Hardware Research Engineer
Design Engineer
Design Engineer
Georgia Institute of Technology
Visvesvaraya Technological University
Recommendations: 0
Verilog
VLSI
ASIC
SystemVerilog
Device Drivers
Embedded Systems
Debugging
FPGA
g****[email protected]
Parv Sharma
Trainee
Hillsboro, Oregon
Trainee
SoC Design Engineer
Library Design Engineer
Research Assistant
Arizona State University
Vellore Institute of Technology
Recommendations: 0
s****[email protected]
Daksha Sharma
Analog Design Engineer
Hillsboro, Oregon
Analog Design Engineer
Graduate Technical Intern
Senior Systems Engineer
Teaching Assistant
University of Michigan
Dhirubhai Ambani Institute of Information and Communication Technology
Recommendations: 0
C
Algorithms
Unix
Verilog
C++
Java
Matlab
Simulink
c****[email protected]
