Top ASIC Design Engineers in Greater San Diego Area
Sriram R
ASIC Design Engineer
Greater San Diego Area
ASIC Design Engineer
Senior Staff Engineer
Physical Design Engineer
Senior Design Engineer
Senior Design Engineer
NIT Hamirpur
Recommendations: 9
ASIC
VLSI
Debugging
SoC
Verilog
Semiconductors
Static Timing Analysis
RTL Design
i****[email protected]
Ashish Banthia
Senior Staff Hardware Engineer
Greater San Diego Area
Senior Staff Hardware Engineer
Member
ASIC Design Engineer
Design Engineer
Intern
Colorado State University
University of Pune
Recommendations: 7
Verilog
ASIC
Integrated Circuit Design
FPGA
VHDL
Digital Signal Processors
TCL
Static Timing Analysis
a****[email protected]
Sri Ganta
ASIC Design Engineer
Greater San Diego Area
ASIC Design Engineer
Associate Technical Director
Sr. Technical Account Manager (Application Engineering)
Design Consultant Engineer/ Sr. Member Technical Staff
Lead Application Engineering Consultant
Principal Member Technical Staff, Customer Product Engineering
Technical Program Manager - Functional (DFx) Specialist
San Jose State University
Sri Venkateswara University
AP Residential School, Bhupathipalem
Recommendations: 7
JTAG
BIST
SoC
ASIC
DFT
Scan
ATP
Verilog
s****[email protected]
Judy Alvarez-Gallardo
Lead ASIC Design Engineer
Greater San Diego Area
Lead ASIC Design Engineer
Staff Design Engineer
Senior Design Engineer
Senior Design Engineer
R&D Hardware Engineer
University of California San Diego
University of California San Diego
Recommendations: 4
Static Timing Analysis
Logic Synthesis
Verilog
j****[email protected]
Jim Henson
Principal ASIC Design Engineer
Greater San Diego Area
Principal ASIC Design Engineer
Principal Design Engineer
Principal Engineer - ASIC Engineering
Principal IC Design Engineer
Sr ASIC Design Engineer
Engineering Consultant
Engineering Design Manager
Engineering Design Manager
Senior ASIC Design Engineer
Design Engineer
West Coast University
San Diego State University-California State University
California Polytechnic State University-San Luis Obispo
Recommendations: 3
Primetime
Verilog
SystemC
VCS
NCSim
ModelSim
C
C++
j****[email protected]
j****[email protected]
Shiv Shankar
Senior Staff Engineer/Manager
Greater San Diego Area
Senior Staff Engineer/Manager
Staff Engineer
ASIC Verification Engineer (Consultant)
USB Design Engineer (Consultant)
ASIC Design Engineer
Madurai Kamaraj University
University of Madras
St. Josephs School, Una (Gujarat)
Recommendations: 1
SystemVerilog
Verilog
ASIC
SoC
FPGA
TCL
Specman
AMBA AHB
s****[email protected]
Karim Abdulla
Digital Design Lead
Greater San Diego Area
Digital Design Lead
Member Technical Staff
Real Estate Entrepreneur
ASIC Engineering Technical Manager
ASIC Design Engineer
University of California San Diego
Harvey Mudd College
West Torrance High School
Recommendations: 1
Mobile Devices
Wireless
ASIC
Entrepreneurship
Engineering Management
Team Leadership
GSM
Engineering
k****[email protected]
Kiran Sastry
Staff Engineer
Greater San Diego Area
Staff Engineer
Senior ASIC Design Engineer
Senior ASIC Design Engineer
VLSI Design Engineer
Research Assistant
Teaching Assistant
Virginia Polytechnic Institute and State University
University of Mysore
Sarada Vilas Junior College
Recommendations: 1
Verilog
Static Timing Analysis
RTL design
ASIC
SoC
Digital Design
Integrated Circuit Design
Formal Verification
k****[email protected]
Sreekanth Allamudi
Trainee Engineer
Greater San Diego Area
Trainee Engineer
Sr Asic Verification Engineer
ASIC Design Engineer
Delhi College of Engineering
Andhra University
Recommendations: 0
Verilog
FPGA
Functional Verification
PCIe
RTL coding
VLSI
ASIC
ModelSim
s****[email protected]
s****[email protected]
Raja Gosula
Director, ASIC Design / Verification
Greater San Diego Area
Director, ASIC Design / Verification
Part Time FPGA Consultant
ASIC Manager
Sr ASIC Design Engineer
Principal Digital ASIC DSP Engineer/Manager
Senior Staff ASIC Engineer/Manager
ASIC Manager
Director, ASIC Design/Verification
Contractor
Digital ASIC DSP Technical Leader II
University of California, Davis
Duke University - The Fuqua School of Business
Case Western Reserve University
Recommendations: 0
Verilog
SystemVerilog
ASIC
SoC
VHDL
IC
Mixed Signal
Microprocessors
Feng Ge
Sr Graphics RTL Design Engineer
Greater San Diego Area
Sr Graphics RTL Design Engineer
Video ASIC Design Engineer
Research Assistant
IC Design Engineer
Illinois Institute of Technology
Fudan University
Recommendations: 0
ASIC
Verilog
Video ASIC
c****[email protected]
Sherry Shao
Senior Staff System Engineer - Graphics Performance
Greater San Diego Area
Senior Staff System Engineer - Graphics Performance
Staff System Engineer - GPU performance
Staff ASIC Design Engineer
Senior ASIC Design Engineer
Senior ASIC design engineer
Tongji University
University of NanJing science and Technology
Recommendations: 0
ASIC
Verilog
Perl
s****[email protected]
Soban Chawre
Staff Engineer
Greater San Diego Area
Staff Engineer
Senior Lead Design Verification Consultant
Member Technical Staff
Senior Design Engineer
Engineer Staff - IC Design
ASIC Design Engineer
University of Mumbai
Recommendations: 0
Verilog
Integrated Circuit Design
RTL design
SystemVerilog
ModelSim
ARM
TCL
FPGA
s****[email protected]
Dan Chuang
Senior Technical Staff
Greater San Diego Area
Senior Technical Staff
Senior Staff Engineer
Senior IC Design Engineer
ASIC Design Engineer
Research & Development Engineer
University of California, Berkeley
California State University-Sacramento
San Francisco State University
Recommendations: 0
DSP
Image Processing
ASIC
FPGA
SoC
Static Timing Analysis
DFT
Digital Design
d****[email protected]
d****[email protected]
Chia Chang
Validation Intern
Greater San Diego Area
Validation Intern
ASIC Design Engineer
Senior Digital Design Engineer
FPGA Prototyping Intern
UCLA
University of California, Los Angeles
Recommendations: 0
Matlab
C
C++
Cadence Virtuoso
Logic Design
Verilog
Simulink
Cadence Spectre
f****[email protected]
Jay Dawes
Senior Manufacturing Engineer, Senior EE
Greater San Diego Area
Senior Manufacturing Engineer, Senior EE
Senior EE Architect
Senior EE Lead Engineer
EE Design Engineer
ASIC Design Engineer
University of California, San Diego
University of California, Davis
University of California, Davis
Recommendations: 0
Design for Manufacturing
Manufacturing...
Contract Manufacturing
Cross-functional Team...
Verilog
SoC
Debugging
PCB design
j****[email protected]
a****[email protected]
Rahul Kodkani
Senior RFIC Design Engineer
Greater San Diego Area
Senior RFIC Design Engineer
RFIC Design Engineer
Interim Engeineer Intern
ASIC Design Engineer (Intern)
University of California San Diego
Bangalore University
West Virginia University
Recommendations: 0
Mixed Signal
Analog
CMOS
Analog Circuit Design
ASIC
IC
RF
Circuit Design
r****[email protected]
r****[email protected]
Antonio Geremia
Principal Systems Engineer
Greater San Diego Area
Principal Systems Engineer
Principal ASIC Design Engineer
Senior Staff Design Engineer
Staff Design Engineer
Staff Design Engineer
engineer
University of San Diego
Recommendations: 0
Static Timing Analysis
Verilog
Semiconductors
Mixed Signal
SoC
SystemVerilog
ASIC
Logic Synthesis
j****[email protected]
j****[email protected]
Perry Virjee
Principal Design Engineer
Greater San Diego Area
Principal Design Engineer
L-3 Communications
Principal ASIC Engineer
Sr ASIC Design Engineer
Cal State Univ. Long Beach
Recommendations: 0
ASIC
FPGA
Digital Signal Processors
Static Timing Analysis
Xilinx
RTL Design
Functional Verification
Analog
p****[email protected]
Manish Dangol
Senior Design Engineer
Greater San Diego Area
Senior Design Engineer
Digital ASIC Design Engineer
Staff Design Engineer
Electronic Design Intern
Senior Staff Design Engineer
Graduate Teaching Assistant
North Dakota State University
Maulana Azad National Institute of Technology
Recommendations: 0
ASIC
RTL design
Verilog
Static Timing Analysis
Integrated Circuit...
SystemVerilog
VHDL
C
m****[email protected]
d****[email protected]
Jerry Alcorn
Senior Digital Engineer
Greater San Diego Area
Senior Digital Engineer
Associate Member, Technical Staff
ASIC Design Engineer
Senior FPGA Engineer
Staff Engineer, Digital Design
Staff Design Engineer
Digital Design Engineer 4
California State University-Sacramento
Recommendations: 0
FPGA
ASIC
Integrated Circuit Design
Xilinx
Altera
Logic Synthesis
VHDL
Verilog
j****[email protected]
Yang Sun
ASIC Design Engineer
Greater San Diego Area
ASIC Design Engineer
ASIC Design Engineer
Senior Staff Engineer
Staff Scientist
R&D
Rice University
Zhejiang University
Recommendations: 0
VLSI
Verilog
ASIC
FPGA
VHDL
SoC
DSP
Signal Processing
Chuck Krause
VP Technology
Greater San Diego Area
VP Technology
ASIC Design Engineer
Digital Design
Digital Design
Digital Design
Digital Design
University of Southern California
Valparaiso University
Recommendations: 0
Digital Signal Processors
Hardware Architecture
Semiconductors
Verilog
Integrated Circuit Design
Bluetooth
ASIC
IC
c****[email protected]
Michael Anderson
Adjunct Professor
Greater San Diego Area
Adjunct Professor
Electrical Engineer
PHD Candidate
ASIC Design Engineer
Founding President
Owner
IC Fabrication Engineer
ASIC Design Engineer
ASIC Design Engineer
Electrical Engineer
University of Michigan
University of Michigan
Recommendations: 0
m****[email protected]
m****[email protected]
Cristian Duroiu
System Architect
Greater San Diego Area
System Architect
Principal Engineer
ASIC Design Engineer
Design Engineer
Assistant Professor
Universitatea „Transilvania” din Brașov
Universitatea „Transilvania” din Brașov
Recommendations: 0
c****[email protected]
Melanie Vrettas
Program Manager
Greater San Diego Area
Program Manager
Customer Program Manager, Emerging Connectivity Solutions
Custome Program Manager, Multimedia Apps Processor Division
Program Manager
Sr ASIC Design Engineer
Member of Technical Staff
Digital IC Designer
Intern
University of Wisconsin-Madison
Recommendations: 0
m****[email protected]
Yingjie Zhou
Senior Principal VLSI Design Engineer/ Manager
Greater San Diego Area
Senior Principal VLSI Design Engineer/ Manager
VLSI Design Engineer
ASIC Design Engineer
IC Design Engineer
Wright State University
Tsinghua University
Recommendations: 0
y****[email protected]
Vikram Haravu
ASIC Design Engineer
Greater San Diego Area
ASIC Design Engineer
Component Design Engineer
Component Design Engineer
Member of Technical Staff, IC Design/Val
Sr Design Engineer
ASIC Design Engineer
Udacity
Rutgers University
Osmania University
Recommendations: 0
