Tejaswi KakarnaASIC Design and Verification Engineer
Greater Boston Area
ASIC Design and Verification Engineer
Graduate Validation Intern
Applications Engineer Intern
Teaching Assistant in Electrical Engineering
Teaching Assistant in Physics PIC LAB
Intern
Lab Assistant
University of North Texas
Jawaharlal Nehru Technological University
Recommendations: 1
UVM
SystemVerilog
Verilog
C++
C
VHDL
Computer Architecture
Perl